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PMN50XP
P-channel TrenchMOS extremely low level FET
Rev. 02 -- 2 October 2007 Product data sheet
1. Product profile
1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features
Low on-state losses Low threshold voltage
1.3 Applications
Battery management Load Switching Battery powered portable equipment Low power DC to DC converters
1.4 Quick reference data
Table 1. VDS ID Quick reference Conditions Tj 25 C; Tj 150 C VGS = -4.5 V; Tsp = 25 C; see Figure 1 and 3 VGS = -4.5 V; ID = -4.7 A; VDS = -10 V; Tj = 25 C; see Figure 9 and 10 VGS = -4.5 V; ID = -2.8 A; Tj = 25 C; see Figure 7 and 8 Min Typ Max -20 -4.8 Unit V A drain-source voltage drain current Symbol Parameter
Dynamic characteristics QGD gate-drain charge 1.3 nC
Static characteristics RDSon drain-source on-state resistance 48 60 m
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
2. Pinning information
Table 2. Pin 1 2 3 4 5 6 Pinning Symbol D D G S D D Description drain drain gate source drain drain
1 2 3
G S
003aaa671
Simplified outline
6 5 4
Graphic Symbol
D
3. Ordering information
Table 3. Ordering information Package Name PMN50XP TSOP6 Description plastic surface-mounted package (TSOP6); 6 leads Version SOT457 Type number
4. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tsp = 25 C Tsp = 25 C; tp 10 s; pulsed Tsp = 25 C; VGS = -4.5 V; see Figure 1 and 3 Tsp = 100 C; VGS = -4.5 V Tsp = 25 C; tp < 10 s; pulsed; see Figure 3 Tsp = 25 C; see Figure 2 Conditions Tj 25 C; Tj 150 C Tj 25 C; Tj 150 C; RGS = 20 k Min -12 -55 -55 Max -20 -20 12 -4.8 -3 -19.4 2.2 150 150 -1.9 -7.5 Unit V V V A A A W C C A A
Source-drain diode
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
2 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
120 Ider (%) 80
03aa25
120 Pder (%) 80
03aa17
40
40
0 0 50 100 150 Tsp (C) 200
0 0 50 100 150 Tsp (C) 200
Ider =
ID ID(25C )
x 100 %
P der =
P tot P tot (25C )
x 100 %
Fig 1. Normalized continuous drain current as a function of solder point temperature
-102 ID (A) -10
Fig 2. Normalized total power dissipation as a function of solder point temperature
001aae333
Limit RDSon = -VDS/-ID
tp = 10 s 100 s
1 ms -1 10 ms DC 100 ms -10-1 -10-1 -1 -10 -102
VDS (V)
Ts p = 25 C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
3 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-sp) Thermal characteristics Parameter Conditions Min Typ Max 55 Unit K/W thermal resistance see Figure 4 from junction to solder point
102
03aj69
Zth(j-sp) (K/W)
= 0.5
0.2 10 0.1 0.05 0.02 single pulse 1 10-4 10-3 10-2 10-1
tp T t P = tp T
1
10
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
6. Characteristics
Table 6. Symbol V(BR)DSS Characteristics Parameter drain-source breakdown voltage Conditions ID = -250 A; VGS = 0 V; Tj = 25 C ID = -250 A; VGS = 0 V; Tj = -55 C VGS(th) gate-source threshold ID = -0.25 mA; VDS = VGS; voltage Tj = 25 C; see Figure 5 and 6 ID = -0.25 mA; VDS = VGS; Tj = 150 C; see Figure 5 and 6 ID = -0.25 mA; VDS = VGS; Tj = -55 C; see Figure 5 and 6 IDSS drain leakage current VDS = -20 V; VGS = 0 V; Tj = 25 C VDS = -20 V; VGS = 0 V; Tj = 70 C Min -20 -18 -0.55 -0.35 Typ -0.75 Max -0.95 -1.1 -1 -5 Unit V V V V V A A
Static characteristics
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
4 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
Table 6. Symbol IGSS RDSon
Characteristics ...continued Parameter gate leakage current drain-source on-state resistance Conditions VGS 12 V; VDS = 0 V; Tj = 25 C VGS 12 V; VDS = 0 V; Tj = 25 C VGS = -4.5 V; ID = -2.8 A; Tj = 25 C; see Figure 7 and 8 VGS = -4.5 V; ID = -2.8 A; Tj = 150 C; see Figure 7 and 8 VGS = -2.5 V; ID = -2.3 A; Tj = 25 C; see Figure 7 and 8 Min Typ -10 -10 48 77 65 Max -100 -100 60 96 80 Unit nA nA m m m
Dynamic characteristics QG(tot) total gate charge ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 C; see Figure 9 and 10 ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 C; see Figure 9 and 10 ID = -4.7 A; VDS = -10 V; VGS = -4.5 V; Tj = 25 C; see Figure 9 and 10 VDS = -20 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 11 VGS = 0 V; VDS = -20 V; f = 1 MHz; Tj = 25 C; see Figure 11 VDS = -20 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 11 RG(ext) = 6 ; RL = 10 ; VDS = -10 V; VGS = -4.5 V; Tj = 25 C RG(ext) = 6 ; RL = 10 ; VDS = -10 V; VGS = -4.5 V; Tj = 25 C VDS = -10 V; RL = 10 ; VGS = -4.5 V; RG(ext) = 6 ; Tj = 25 C RG(ext) = 6 ; RL = 6 ; VDS = -10 V; VGS = -4.5 V; Tj = 25 C VDS = -10 V; ID = -4.7 A; Tj = 25 C; see Figure 9 and 10 IS = -1.7 A; VGS = 0 V; Tj = 25 C 10 nC
QGS
gate-source charge
-
2.2
-
nC
QGD
gate-drain charge
-
1.3
-
nC
Ciss
input capacitance
-
1020
-
pF
Coss
output capacitance
-
140
-
pF
Crss
reverse transfer capacitance turn-on delay time
-
100
-
pF
td(on)
-
8.5
-
ns
tr
rise time
-
7.5
-
ns
td(off)
turn-off delay time
-
82
-
ns
tf
fall time
-
35
-
ns
VGS(pl)
gate-source plateau voltage source-drain voltage
-
-1.6
-
V
Source-drain diode VSD trr -0.77 -1.2 V ns reverse recovery time IS = 3.5 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 20 V; Tj = 25 C
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
5 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
-1.2 VGS(th) (V) -0.8
03ar95
-10-3 ID (A) -10-4 min typ
001aae334
max
typ
min
-10-5
max
-0.4
0 -60
0
60
120
Tj (C)
180
-10-6
0
-0.2
-0.4
-0.6
-0.8 -1.0 VGS (V)
ID = 0.25 m A; VDS = VGS
T j = 25 C; VDS = 5 V
Fig 5. Gate-source threshold voltage as a function of junction temperature
150 RDSon (m) 120 -2.5 90 -3 -3.5 -4.5
03aq05
Fig 6. Sub-threshold drain current as a function of gate-source voltage
2 a 1.5
03aq10
VGS (V) = -2
1
60
0.5
30
0 0 -5 -10 -15 ID (A) -20
0 -60
0
60
120
Tj (C)
180
T j = 25 C
a=
R DSon R DSon (25C )
Fig 7. Drain-source on-state resistance as a function of drain current; typical values
Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
6 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
-5 VGS (V) -4 ID = -4.7 A Tj = 25 C VDS = -10 V
03aq09
VDS ID VGS(pl)
-3
-2
VGS(th)
-1
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
0 0 4 8 QG (nC) 12
QGS
ID = 4.7 A; T j = 25 C; VDS = 10 V
Fig 9. Gate-source voltage as a function of gate charge; typical values
104 C (pF) 103
Fig 10. Gate charge waveform definitions
001aae335
Ciss
102
Coss Crss
10 -10-1
-1
-10
VDS (V)
-102
VGS = 0 V; f = 1 M H z
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
7 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
7. Package outline
Plastic surface-mounted package (TSOP6); 6 leads SOT457
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A A1 c
1
2
3
Lp
e
bp
wM B detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT457
REFERENCES IEC JEDEC JEITA SC-74
EUROPEAN PROJECTION
ISSUE DATE 05-11-07 06-03-16
Fig 12. Package outline SOT457 (TSOP6)
PMN50XP_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
8 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
8. Revision history
Table 7. Revision history Release date 20071002 Data sheet status Product data sheet Change notice Supersedes PMN50XP_1 Document ID PMN50XP_2 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the company name where appropriate. Product data sheet -
PMN50XP_1
20060123
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
9 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PMN50XP_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 2 October 2007
10 of 11
NXP Semiconductors
PMN50XP
P-channel TrenchMOS extremely low level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 October 2007 Document identifier: PMN50XP_2

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